The ever increasing number of transistors that can be crammed onto a single integrated circuit device has given rise to the system on a chip (known as “SOC”). Unfortunately, as useful as SOCs are, as they continue to increase in complexity, the expense, delay and difficulty in testing them has also increased. This situation has created an ever increasing burden on the chip manufacturer and others to test SOCs and other integrated circuits (known as “ICs”) without letting the associated cost of testing become prohibitive.
Wafer sort is a phrase that refers to testing of ICs at the wafer stage. “Wafer” refers to a thin disk of semiconducting material such as silicon, silicon germanium, gallium arsenide, indium phosphide onto which integrated circuits have been created, typically through etching and deposition processes. Currently, wafers are typically between 6 inches and 12 inches in diameter.
Each wafer includes a number of discrete ICs often in square or rectangular shapes and packed onto the surface of the wafer. These ICs are called “die” at this point before they are physically cut into individual ICs and packaged. The IC manufacturer tests integrated circuits while they are still physically part of the wafer.
To test the die, a machine called a wafer prober positions a finished wafer very accurately below a probe card. The probe card contains many probes, typically one for each pad on each die. The probes may be needle-like or may use a different approach, such as a membrane technology. The probes must be physically arranged in precise correspondence to the pads on the particular die to be tested in order to make electrical contact with all the pads of interest. The die contain pads for physically and electrically connecting the IC to its pins in its package or perhaps to other devices. More complicated ICs, like the microprocessor-based SOCs, often contain dozens or even hundreds of pads corresponding to the number of pins such devices require. The probe card itself is typically an annular printed circuit board between 6″ and 12″ in diameter Under control of the wafer prober, the wafer is pressed against the probe card so that electrical contact is made between the pads of the die and the probes. A series of electrical signals, including power, is fed through the probes into some of the pads for testing the die. Resulting electrical signals are fed back through other pads into their corresponding probes and back into the probe card for analysis. When the testing of that die is complete, the wafer prober positions the wafer such that electrical contact is made between the probe card and the next die to be tested.
Typically, one die is tested at a time, although in some cases, the probe card may connect with more than one die, allowing more than one die to be tested at the same time. This approach is limited by the number of probes that can economically be attached to one card as well as the size of the probe card and the size and weight of associated electronics used to control the probe card.
In current IC wafer sort testers, the probe card is connected through special connectors on a fixture board to pin electronics in a test head. The fixture board is physically and electrically attached to the probe card and test head. In one embodiment, there are special connectors on or interfaced to the fixture board called pogo pins through which the fixture board is connected to the probes on the probe card. In this way, the test electronics in the tester are connected through the probes on the probe card to the pads of the die, providing the electrical connection that is needed to test the die.
For mechanical stability, the test head attaches to the mechanical frame of the wafer prober. Because the typical test head is very large and heavy, they typically are mounted on large positioner machines that use counter-balancing weights to make it easier to manipulate the test head.
Traditional IC wafer sort testers, also known as automatic test equipment (“ATE”) have a large test head. The size of the test head ranges from the size of the typical clothes dryer to something that can be several times that large. In the past few years, there have been some integrated circuit testers introduced that have the entire tester in the test head. However even in those cases, the test head is very large, consuming large amounts of floor space in costly clean rooms in IC factories.
In addition to being very large, the test heads of traditional testers are very heavy, requiring expensive, specialized positioning equipment that utilizes counter-balancing weights to allow the test head to be moved and positioned as needed.
The traditional approach to wafer sort using ATEs described above has several disadvantages:
1. Current ATEs takes up a lot of expensive floor space (often 25 square feet or more)
2. The typical ATE test head is very bulky and massive, and is difficult to manipulate.
3. The process of disconnecting and reconnecting the test head to switch probe cards and from the wafer prober can take several minutes which reduces test-floor productivity and throughput.
4. When the traditional test head is attached to the ATE, the operator does not have direct access to the probe card. He cannot easily examine and correct problems.
5. The traditional test head (and ATE system) is very expensive, impacting the cost associated with producing the ICs being tested.
6. Interfacing the large test head to the probes on the probe card requires signal lengths from the tester pins to the device pads of several inches. The length of this path results in a significant loading effect on both the tester and the device's output pins, resulting in degradation of signal quality. This loading also results in a need for testers to have high-current drivers that can overcome the loading effect of the long signal paths. That, in turn, increases power consumption and the need for heat dissipation.
7. Pogo pin connections are prone to failure due to effects such as oxidation and breakage of the pogo pin springs.
To some extent, each of these problems have been exacerbated in recent years with the increasing complexity of ICs in general and SOCs in particular. The combination of current testing methodology with the increasing complexity of SOCs in particular have meant that testing an increasing amount of pads, signals and circuitry, requires an increasing amount of time, space, power and ultimately money. This combination of traditional IC testing paradigms with chips of ever-increasing complexity has made thorough IC testing ever more difficult and expensive. It would be advantageous to address these difficulties.